Magnetic random access memory (MRAM) using spin-induced switching is a strong candidate for providing a dense and fast non-volatile storage solution for future memory applications. Each MRAM includes an array of memory cells. FIG. 1 shows a schematic view of MRAM cell employing a spin-induced writing mechanism according to a prior art. The cell comprises a magnetoresistive element (or magnetic tunnel junction) J, a selection transistor T, a bit line BL, a word line WL, and a source line SL. The bit and word lines are formed in different layers and intersect each other in space. The magnetoresistive (MR) element J and the selection transistor T are connected in series and disposed in a vertical space between intersecting bit and word lines. They are connected to the source line SL at one end and to the bit line BL at another end. The word line is connected to a gate terminal of the selection transistor T. The MR element J comprises at least a pinned (or reference) layer 12 with a fixed direction of magnetization (shown by a solid arrow), a free (or storage) layer 16 with a reversible magnetization direction (shown by a dashed arrow), and a tunnel barrier layer 14 disposed between the pinned and free magnetic layers. The direction of the magnetization in the free layer 16 can be controlled by a direction of a spin-polarized current IS running through the element J in a direction perpendicular to a film surface. Resistance of the MR element depends on a mutual orientation of the magnetizations in the magnetic layers 12 and 16. The resistance is low when the magnetizations in the layers 12 and 16 are parallel to each other (logic “0”), and high when the magnetizations are antiparallel (logic “1”). Difference in the resistance between two magnetic states can exceed several hundred percent at room temperature.
FIG. 2 shows a circuit diagram of a portion of MRAM 20 with spin-induced switching according to a prior art. The MRAM 20 includes an array 22 of memory cells C11-C33 (other cells are not shown) disposed in a vertical space between pluralities of parallel bits and word lines at their intersections. Each memory cell comprises an MR element J and transistor T connected in series. A plurality of parallel bit lines BL1-BL3 is connected to a bit line driver 24. A plurality of the word lines WL1-WL3 is connected to a word line driver 26. A plurality of the parallel source lines SL1-SL3 is connected to a source line driver 28. Selection of a memory cell in the array 22 is provided by applying a suitable signal to appropriate bit and word lines. For instance, to select the memory cell C22 that is located at the intersection of the bit line BL2 and the word line WL2, the signals need to be applied to these lines through the drivers 24 and 26, respectively.
Cell size is one of key parameters of the MRAM. It substantially depends on the size and number of selection transistors supplying a spin-polarized write current to a MR element. The number of the transistors controlling the write current usually vary from one to two per a MR element. It depends on a saturation current of a selection transistor and magnitude of the spin-polarized current required to cause switching of the MR element. Frequently, especially for MR elements having in-plane magnetization in magnetic layers, one selection transistor cannot provide the required spin-polarized current due to its saturation. This obstacle prevents the MRAM cell size reduction.
Another important parameter of MRAM is a write speed. The write speed depends on a magnitude of the spin-polarized current running through the MR element. High speed (short duration of the write current pulse) requires higher magnitude of the spin-polarized current that can be limited by the saturation current of the selection transistor or by a breakdown of the tunnel barrier layer.
The present disclosure addresses to the above problems.